Electronic designs for large systems may include millions of gates and megabits of embedded memory. Of the tasks required in managing and optimizing electronic designs on a target device, synthesis, placement, and routing utilizing available resources can be among the most challenging and time consuming. The complexity of large systems often requires the use of electronic design automation (EDA) tools to manage and optimize designs. EDA tools perform the time-consuming tasks of synthesis, placement, and routing on a target device.
The physical design process of modern high-density, high performance digital circuits in field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs) technologies requires the ability to iterate rapidly during design and debugging stages. State of the art designs which integrate together hundreds of design modules may require many hours of time to compile. Since designs are recompiled frequently during development and debugging, it is highly desirable to reduce compilation times. Additionally, EDA tools use heuristic algorithms that can produce different results given a different set of conditions. This is known as the “seed effect”. To mitigate this seed effect, which can cause large variations in circuit quality, designers often compile the same version of their design multiple times using slightly different input conditions to meet performance requirements.
EDA tools have responded to these challenges by integrating incremental design features into their computer aided design (CAD) flows. Incremental design reuses results from previous compilation for unmodified portions of the design. Incremental design can reduce overall design time by 1) speeding up individual compilation, and 2) preserving the performance of unmodified portions of the design.
In order to perform incremental design, an existing design must be divided into partitions. For many EDA tools, dividing a system design into partitions is done manually by the designer. Since modern designs may have hundreds or thousands of modules to partition, the task of partitioning a design could be time consuming for a designer. In addition, poor partitioning choices can degrade circuit quality significantly and often negates the benefits of using incremental design.